AD15700SLASHPCB datasheet(5/44 Pages) AD

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REV. A

AD15700

–5–

1.6mA

IOL

IOH

500mA

60pF

TO OUTPUT

IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE THE LOAD IS 60pF MAXIMUM.

1.4V

Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF

0.8V

tDELAY

0.8V

Figure 2. Voltage Reference Levels for Timing

Table II. Serial Clock Timings in Master Read after Convert

DIVSCLK[1]

0011

DIVSCLK[0]

Symbol

0101Unit

SYNC to SCLK First Edge Delay Minimum

t18

420

2020ns

Internal SCLK Period Minimum

t19

100

200

Internal SCLK Period Maximum

t19

140

280

Internal SCLK HIGH Minimum

t20

100

Internal SCLK LOW Minimum

t21

924

4999ns

SDOUT Valid Setup Time Minimum

t22

4.5

SDOUT Valid Hold Time Minimum

t23

2430

89ns

SCLK Last Edge to SYNC Delay Minimum

t24

360

140

300

BUSY HIGH Width Maximum (Warp)

t28

1.5

5.25

BUSY HIGH Width Maximum (Normal)

t28

1.75

2.25

3.25

5.5

BUSY HIGH Width Maximum (Impulse)

t28

2.5

3.5

5.75

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