AD15700SLASHPCB datasheet(11/44 Pages) AD

11 / 44 page

REV. A

AD15700

–11–

ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42)

Pin No.

Mnemonic

Type

Description

H9, J8,

AGND_ADC

Analog Power Ground Pin

J9, M12

AVDD

Input Analog Power Pin. Nominally 5 V.

BYTESWAP

Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB

is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is

output on D[7:0].

OB/

Straight Binary/Binary Twos Complement. When OB/

2C is HIGH, the digital output

is straight binary; when LOW, the MSB is inverted, resulting in a twos complement

output from its internal shift register.

WARP

Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,

the maximum throughput is achievable, and a minimum conversion rate must be applied

in order to guarantee full specified accuracy. When LOW, full accuracy is maintained

independent of the minimum conversion rate.

IMPULSE

Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.

In this mode, the power dissipation is approximately proportional to the sampling rate.

SER/

PAR

Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH,

the Serial Interface Mode is selected and some bits of the DATA bus are used as a

serial port.

M9, L10

D[0:1]

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/

PAR is HIGH, these

outputs are in high impedance.

M10, L11 D[2:3] or

DI/O

When SER/

PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the

DIVSCLK[0:1]

serial master read DIVSCLK[0:1] after Convert Mode. These inputs, part of the Serial

Port, are used to slow down, if desired, the internal serial clock that clocks the data output.

In the other serial modes, these inputs are not used.

M11

D[4] or EXT/

INT

DI/O

When SER/

PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output

Bus. When SER/

PAR is HIGH, this input, part of the Serial Port, is used as a digital

select input for choosing the internal or an external data clock, called, respectively, Master

and Slave Mode. With EXT/

INT tied LOW, the internal clock is selected on SCLK

output. With EXT/

INT set to a logic HIGH, output data is synchronized to an external

clock signal connected to the SCLK input and the external clock is gated by

CS_ADC.

L12

D[5] or INVSYNC

DI/O

When SER/

PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output

Bus. When SER/

PAR is HIGH, this input, part of the Serial Port, is used to select the

active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,

SYNC is active LOW.

K11

D[6] or INVSCLK

DI/O

When SER/

PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output

Bus. When SER/

PAR is HIGH, this input, part of the Serial Port, is used to invert the

SCLK signal. It is active in both Master and Slave Mode.

K12

D[7] or RDC/SDIN

DI/O

When SER/

PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output

Bus. When SER/

PAR is HIGH, this input, part of the serial port, is used as either an

external data input or a read mode selection input, depending on the state of EXT/

INT.

When EXT/

INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain

the conversion results from two or more ADCs onto a single SDOUT line. The digital

data level on SDIN is output on DATA with a delay of 16 SCLK periods after the

initiation of the read sequence. When EXT/

INT is LOW, RDC/SDIN is used to select

the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT

during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT

only when the conversion is complete.

J10

OGND

Input/Output Interface Digital Power Ground

J11

OVDD

Input/Output Interface Digital Power. Nominally at the same supply as the supply of

the host interface (5 V or 3.3 V).

J12

DVDD

Digital Power. Nominally at 5 V.

AD15700/PCB Datenblatt(PDF) 11 Page - Analog Devices

AD15700/PCB Datenblatt(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datenblatt Download

Link URL