WM8281ECSSLASHR datasheet(275/392 Pages) CIRRUS

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WM8281

Rev 4.0

275

FREQUENCY LOCKED LOOP (FLL)

Two integrated FLLs are provided to support the clocking requirements of the WM8281. These can be

enabled and configured independently according to the available reference clocks and the application

requirements. The reference clock may be a high frequency (eg. 12.288MHz) or low frequency (eg.

32.768kHz).

The FLL is tolerant of jitter and may be used to generate a stable output clock from a less stable input

reference. The FLL characteristics are summarised in “Electrical Characteristics”. Note that the FLL

can be used to generate a free-running clock in the absence of an external reference source. This is

described in the “Free-Running FLL Mode” section below. Configurable spread-spectrum modulation

can be applied to the FLL outputs, to control EMI effects.

Each of the FLLs comprises two sub-systems -

the ‘main’ loop and the ‘synchroniser’ loop; these can

be used together to maintain best frequency accuracy and noise (jitter) performance across multiple

use-cases. The two-loop design enables the FLL to synchronise effectively to an input clock that may

be intermittent or noisy, whilst also achieving the performance benefits of a stable clock reference that

may be asynchronous to the audio data.

The main loop takes a constant and stable clock reference as its input. For best performance, a high

frequency (eg. 12.288MHz) reference is recommended. The main FLL loop will free-run without any

clock reference if the input signal is removed; it can also be configured to initiate an output in the

absence of any reference signal.

The synchroniser loop takes a separate clock reference as its input. The synchroniser input may be

intermittent (eg. during voice calls only). The FLL uses the synchroniser input, when available, as the

frequency reference. To achieve the designed performance advantage, the synchroniser input must

be synchronous with the audio data.

Note that, if only a single clock input reference is used, this must be configured as the main FLL input

reference. The synchroniser should be disabled in this case.

The synchroniser loop should only be used when the main loop clock reference is present. If the input

reference to the main FLL is intermittent, or may be interrupted unexpectedly, then the synchroniser

should be disabled.

The FLL is enabled using the FLLn_ENA register bit (where n = 1 or 2 for the corresponding FLL).

The FLL Synchroniser is enabled using the FLLn_SYNC_ENA register bit.

Note that the other FLL registers should be configured before enabling the FLL; the FLLn_ENA and

FLLn_SYNC_ENA register bits should be set as the final step of the FLLn enable sequence.

The FLL supports configurable free-running operation, using the FLLn_FREERUN register bits

described in the next section. Note that, once the FLL output has been established, the FLL will

always free-run when the input reference clock is stopped, regardless of the FLLn_FREERUN bits.

To disable the FLL while the input reference clock has stopped, the respective FLLn_FREERUN bit

must be set to ‘1’, before setting the FLLn_ENA bit to ‘0’.

When changing FLL settings, it is recommended that the digital circuit be disabled via FLLn_ENA and

then re-enabled after the other register settings have been updated. When changing the input

reference frequency FREF, it is recommended that the FLL be reset by setting FLLn_ENA to 0.

Note that some of the FLL configuration registers can be updated while the FLL is enabled, as

described below. As a general rule, however, it is recommended to configure the FLL (and FLL

Synchroniser, if applicable), before setting the corresponding _ENA register bit(s).

The FLL configuration requirements are illustrated in Figure 71.

WM8281ECS/R Datenblatt(PDF) 275 Page - Cirrus Logic

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