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WM8281ECS/R Datenblatt(PDF) 284 Page - Cirrus Logic

Teilenummer WM8281ECS/R
Bauteilbeschribung  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 284 Page - Cirrus Logic

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WM8281
284
Rev 4.0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R409
(0199h)
FLL2
Control 7
5:2
FLL2_GAIN [3:0]
0000
FLL2 Gain
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 to 1111 = 256
R417
(01A1h)
FLL2
Synchroni
ser 1
0
FLL2_SYNC_EN
A
0
FLL2 Synchroniser Enable
0 = Disabled
1 = Enabled
This should be set as the final step of the
FLL2 synchroniser enable sequence, ie.
after the other synchroniser registers have
been configured.
R418
(01A2h)
FLL2
Synchroni
ser 2
9:0
FLL2_SYNC_N
[9:0]
000h
FLL2 Integer multiply for FSYNC
(LSB = 1)
R419
(01A3h)
FLL2
Synchroni
ser 3
15:0
FLL2_SYNC_TH
ETA [15:0]
0000h
FLL2 Fractional multiply for FSYNC
This field sets the numerator (multiply)
part of the FLL2_SYNC_THETA /
FLL2_SYNC_LAMBDA ratio.
Coded as LSB = 1.
R420
(01A4h)
FLL2
Synchroni
ser 4
15:0
FLL2_SYNC_LA
MBDA [15:0]
0000h
FLL2 Fractional multiply for FSYNC
This field sets the denominator (dividing)
part of the FLL2_SYNC_THETA /
FLL2_SYNC_LAMBDA ratio.
Coded as LSB = 1.
R421
(01A5h)
FLL2
Synchroni
ser 5
10:8
FLL2_SYNC_FR
ATIO [2:0]
000
FLL2 Synchroniser FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
R422
(01A6h)
FLL2
Synchroni
ser 6
7:6
FLL2_SYNCCLK
_DIV [1:0]
00
FLL2 Synchroniser Clock Reference
Divider
00 = 1
01 = 2
10 = 4
11 = 8
MCLK (or other input reference) must be
divided down to <=13.5MHz.
For lower power operation, the reference
clock can be divided down further if
desired.



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