WM8281ECSSLASHR datasheet(283/392 Pages) CIRRUS

283 / 392 page

WM8281

Rev 4.0

283

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R403

(0193h)

FLL2

Control 3

15:0

FLL2_THETA

[15:0]

0018h

FLL2 Fractional multiply for FREF

This field sets the numerator (multiply)

part of the FLL2_THETA / FLL2_LAMBDA

ratio.

Coded as LSB = 1.

If updated while the FLL is enabled, the

new value is only effective

when a ‘1’ is

written to FLL2_CTRL_UPD.

R404

(0194h)

FLL2

Control 4

15:0

FLL2_LAMBDA

[15:0]

007Dh

FLL2 Fractional multiply for FREF

This field sets the denominator (dividing)

part of the FLL2_THETA / FLL2_LAMBDA

ratio.

Coded as LSB = 1.

R405

(0195h)

FLL2

Control 5

11:8

FLL2_FRATIO

[3:0]

FLL2 FVCO clock divider

0h = 1

1h = 2

2h = 3

3h = 4

…

Fh = 16

3:1

FLL2_OUTDIV

[2:0]

110

FLL2 FOUT clock divider

000 = Reserved

001 = Reserved

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5

110 = Divide by 6

111 = Divide by 7

(FOUT = FVCO / FLL2_OUTDIV)

R406

(0196h)

FLL2

Control 6

7:6

FLL2_REFCLK_

DIV [1:0]

FLL2 Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be

divided down to <=13.5MHz.

For lower power operation, the reference

clock can be divided down further if

desired.

3:0

FLL2_REFCLK_S

0000

FLL2 Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

0100 = FLL1

0101 = FLL2

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1100 = AIF1RXLRCLK

1101 = AIF2RXLRCLK

1110 = AIF3RXLRCLK

All other codes are Reserved

WM8281ECS/R Datenblatt(PDF) 283 Page - Cirrus Logic

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