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WM8281ECS/R Datenblatt(PDF) 282 Page - Cirrus Logic

Teilenummer WM8281ECS/R
Bauteilbeschribung  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 282 Page - Cirrus Logic

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WM8281
282
Rev 4.0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R390
(0186h)
FLL1
Synchroni
ser 6
7:6
FLL1_SYNCCLK
_DIV [1:0]
00
FLL1 Synchroniser Clock Reference
Divider
00 = 1
01 = 2
10 = 4
11 = 8
MCLK (or other input reference) must be
divided down to <=13.5MHz.
For lower power operation, the reference
clock can be divided down further if
desired.
3:0
FLL1_SYNCCLK
_SRC
0000
FLL1 Synchroniser Clock source
0000 = MCLK1
0001 = MCLK2
0011 = SLIMCLK
0100 = FLL1
0101 = FLL2
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1100 = AIF1RXLRCLK
1101 = AIF2RXLRCLK
1110 = AIF3RXLRCLK
All other codes are Reserved
R391
(0187h)
FLL1
Synchroni
ser 7
5:2
FLL1_SYNC_GAI
N [3:0]
0000
FLL1 Synchroniser Gain
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 to 1111 = 256
0
FLL1_SYNC_DF
SAT
1
FLL1 Synchroniser Bandwidth
0 = Wide bandwidth
1 = Narrow bandwidth
Table 106 FLL1 Register Map
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R401
(0191h)
FLL2
Control 1
0
FLL2_ENA
0
FLL2 Enable
0 = Disabled
1 = Enabled
This should be set as the final step of the
FLL2 enable sequence, ie. after the other
FLL registers have been configured.
R402
(0192h)
FLL2
Control 2
15
FLL2_CTRL_UP
D
0
FLL2 Control Update
Write ‘1’ to apply the FLL2_N and
FLL2_THETA register settings.
(Only valid when FLL2_ENA=1)
9:0
FLL2_N [9:0]
008h
FLL2 Integer multiply for FREF
(LSB = 1)
If updated while the FLL is enabled, the
new value is only effective
when a ‘1’ is
written to FLL2_CTRL_UPD.



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