WM8281ECSSLASHR datasheet(281/392 Pages) CIRRUS

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WM8281

Rev 4.0

281

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:0

FLL1_REFCLK_S

0000

FLL1 Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

0100 = FLL1

0101 = FLL2

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1100 = AIF1RXLRCLK

1101 = AIF2RXLRCLK

1110 = AIF3RXLRCLK

All other codes are Reserved

R377

(0179h)

FLL1

Control 7

5:2

FLL1_GAIN [3:0]

0000

FLL1 Gain

0000 = 1

0001 = 2

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000 to 1111 = 256

R385

(0181h)

FLL1

Synchroni

ser 1

FLL1_SYNC_EN

FLL1 Synchroniser Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the

FLL1 synchroniser enable sequence, ie.

after the other synchroniser registers have

been configured.

R386

(0182h)

FLL1

Synchroni

ser 2

9:0

FLL1_SYNC_N

[9:0]

000h

FLL1 Integer multiply for FSYNC

(LSB = 1)

R387

(0183h)

FLL1

Synchroni

ser 3

15:0

FLL1_SYNC_TH

ETA [15:0]

0000h

FLL1 Fractional multiply for FSYNC

This field sets the numerator (multiply)

part of the FLL1_SYNC_THETA /

FLL1_SYNC_LAMBDA ratio.

Coded as LSB = 1.

R388

(0184h)

FLL1

Synchroni

ser 4

15:0

FLL1_SYNC_LA

MBDA [15:0]

0000h

FLL1 Fractional multiply for FSYNC

This field sets the denominator (dividing)

part of the FLL1_SYNC_THETA /

FLL1_SYNC_LAMBDA ratio.

Coded as LSB = 1.

R389

(0185h)

FLL1

Synchroni

ser 5

10:8

FLL1_SYNC_FR

ATIO [2:0]

000

FLL1 Synchroniser FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

WM8281ECS/R Datenblatt(PDF) 281 Page - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 281 Page - Cirrus Logic

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