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WM8281ECS/R Datenblatt(PDF) 289 Page - Cirrus Logic |
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WM8281ECS/R Datenblatt(HTML) 289 Page - Cirrus Logic |
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289 / 392 page ![]() WM8281 Rev 4.0 289 EXAMPLE FLL SETTINGS Table 110 provides example FLL settings for generating 147.456MHz SYSCLK from a variety of low and high frequency reference inputs. FSOURCE FOUT (MHz) FREF Divider N.K FRATIO FVCO ( MHz) OUTDIV FLLn_N FLLn_ THETA FLLn_ LAMBDA 32.000 kHz 147.456 1 204.8 15 294.912 2 0CCh 0004h 0005h 32.768 kHz 147.456 1 187.5 16 294.912 2 0BBh 0001h 0002h 48 kHz 147.456 1 136.5333 15 294.912 2 088h 0008h 000Fh 128 kHz 147.456 1 109.4173 7 294.912 2 06Dh 0005h 0007h 512 kHz 147.456 1 38.4 5 294.912 2 026h 0002h 0005h 1.536 MHz 147.456 1 21.3333 3 294.912 2 015h 0001h 0003h 3.072 MHz 147.456 1 10.6667 3 294.912 2 00Ah 0002h 0003h 11.2896 MHz 147.456 1 8.7075 1 294.912 2 008h 0068h 0093h 12.000 MHz 147.456 1 8.192 1 294.912 2 008h 0018h 007Dh 12.288 MHz 147.456 2 5.3333 3 294.912 2 005h 0001h 0003h 13.000 MHz 147.456 1 7.5618 1 294.912 2 007h 0391h 0659h 19.200 MHz 147.456 2 10.24 1 294.912 2 00Ah 0006h 0019h 24 MHz 147.456 2 8.192 1 294.912 2 008h 0018h 007Dh 26 MHz 147.456 2 7.5618 1 294.912 2 007h 0391h 0659h 27 MHz 147.456 2 7.2818 1 294.912 2 007h 013Dh 0465h FOUT = (FSOURCE / FREF Divider) * 3 * N.K * FRATIO / OUTDIV The values of N and K are contained in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above. See Table 106 and Table 107 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers. Table 110 Example FLL Settings Note that the odd-numbered FRATIO division is not possible on the FLL Synchroniser circuit. Table 111 provides alternative settings for the FLL Synchroniser for the affected examples. In all cases, note that the register coding of FLLn_FRATIO is different to FLLn_SYNC_FRATIO. FSOURCE FOUT (MHz) FREF Divider N.K FRATIO FVCO ( MHz) OUTDIV FLLn_N FLLn_ THETA FLLn_ LAMBDA 32.000 kHz 147.456 1 192 16 294.912 2 0C0h 48 kHz 147.456 1 128 16 294.912 2 080h 128 kHz 147.456 1 96 8 294.912 2 060h 512 kHz 147.456 1 96 2 294.912 2 060h 1.536 MHz 147.456 1 64 1 294.912 2 040h 3.072 MHz 147.456 1 32 1 294.912 2 020h 12.288 MHz 147.456 1 8 1 294.912 2 008h FOUT = (FSOURCE / FREF Divider) * 3 * N.K * FRATIO / OUTDIV The values of N and K are contained in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above. See Table 106 and Table 107 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers. Table 111 Example FLL Synchroniser Settings |
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