WM8281ECSSLASHR datasheet(290/392 Pages) CIRRUS

290 / 392 page

WM8281

290

Rev 4.0

CONTROL INTERFACE

The WM8281 is controlled by writing to its control registers. Readback is available for all registers.

Two independent Control Interfaces are provided, giving flexible capability as described below. Note

that the SLIMbus interface also supports read/write access to the WM8281 control registers - see

“SLIMbus Interface Control”.

Note that the Control Interface function can be supported with or without system clocking. Where

applicable, the register map access is synchronised with SYSCLK in order to ensure predictable

operation of cross-

domain functions. See “Clocking and Sample Rates” for further details of Control

Interface clocking.

When SYSCLK is present and enabled, register access is possible on all of the Control Interfaces

(including SLIMbus) simultaneously.

When SYSCLK is disabled, then register access will only be supported on whichever interface (I2C,

SPI, or SLIMbus) is the first to attempt any register access after SYSCLK has stopped. Full access via

all interfaces will be restored when SYSCLK is enabled.

The WM8281 executes a Boot Sequence following Power-On Reset (POR), Hardware Reset,

Software Reset or Wake-Up (from Sleep mode). Note that Control Register writes should not be

attempted until the Boot Sequence has completed. See “Power-On Reset (POR)” for further details.

The WM8281 performs automatic checks to confirm that the control interface does not attempt a Read

or Write operation to an invalid register address. The Control Interface Address Error condition can be

monitored using the GPIO

and/or Interrupt functions. See “General Purpose Input / Output” and

“Interrupts” for further details.

Control Interface 1 can be configured as a 2-wire (I2C) interface or 4-wire (SPI) interface. This is

determined by the logic level on the CIF1MODE pin, as shown in Table 112.

All of the CIF1 interface pins are referenced to the DBVDD1 power domain.

CIF1MODE

CONTROL INTERFACE MODE

DESCRIPTION

Logic 0

2-wire (I2C) mode

CIF1SCLK is the interface clock input

CIF1SDA is the bi-directional data pin

Logic 1

4-wire (SPI) mode

CIF1SCLK is the interface clock input

CIF1MOSI is the data input pin

CIF1MISO is the data output pin

CIF1SS

¯¯¯¯¯¯¯

is the ‘slave select’ input

Table 112 Control Interface 1 Mode Selection

The CIF1ADDR and CIF1SS

¯¯¯¯¯¯¯ functions are implemented on a shared pin. In 2-wire (I2C) mode, the

CIF1ADDR input selects the Device ID, as described in Table 114. In 4-wire (SPI) mode, the CIF1SS

¯¯¯¯¯¯¯

input provides the ‘Slave Select’ function.

The CIF1MISO function shares the same pin as GPIO4

(see “General Purpose Input / Output”). The

CIF1MISO function is selected by default; this is determined by the SPI_GPIO register bit as

described in Table 113.

Control Interface 2 operates as a 2-wire (I2C) interface only.

The CIF2 interface pins are referenced to the DBVDD2 power domain.

A detailed description of the 2-wire (I2C) interface and 4-wire (SPI) interface modes is provided in the

following sections. The Control Interface configuration registers are described in Table 113.

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