WM8281ECSSLASHR datasheet(291/392 Pages) CIRRUS

291 / 392 page

WM8281

Rev 4.0

291

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Ctrl IF SPI

CFG 1

SPI_CFG

CIF1MISO pin configuration

(applies to SPI mode only)

0 = CMOS

1 = Wired ‘OR’.

SPI_GPIO

CIF1MISO / GPIO4 pin function select

0 = GPIO4

1 = CIF1MISO

1:0

SPI_AUTO_INC

[1:0]

CIF1 SPI Address auto-increment select

00 = Disabled

01 = Increment by 1 on each access

10 = Increment by 2 on each access

11 = Increment by 3 on each access

R9 (09h)

Ctrl IF

I2C1 CFG

1:0

I2C1_AUTO_IN

C [1:0]

CIF1 I2C Address auto-increment select

00 = Disabled

01 = Increment by 1 on each access

10 = Increment by 2 on each access

11 = Increment by 3 on each access

R10 (0Ah)

Ctrl IF

I2C2 CFG

1:0

I2C2_AUTO_IN

C [1:0]

CIF2 I2C Address auto-increment select

00 = Disabled

01 = Increment by 1 on each access

10 = Increment by 2 on each access

11 = Increment by 3 on each access

R11 (0Bh)

Ctrl IF

I2C1 CFG

6:0

I2C1_DEV_ID

[6:0]

1Ah

CIF1 Device ID

(Read Only)

Note that this 7-bit field identifies bits [7:1]

of the CIF1 I2C device ID. The read/write

bit is appended to these 7 bits.

R12 (0Ch)

Ctrl IF

I2C2 CFG

6:0

I2C2_DEV_ID

[6:0]

1Ah

CIF2 Device ID

Note that this 7-bit field identifies bits [7:1]

of the CIF2 I2C device ID. The read/write

bit is appended to these 7 bits.

R3105

(0C21h)

Misc Pad

Ctrl 2

ADDR_PD

CIF1ADDR Pull-down enable

0 = Disabled

1 = Enabled

Table 113 Control Interface Configuration

2-WIRE (I2C) CONTROL MODE

The 2-wire (I2C) Control Interface mode is supported on CIF1 and CIF2, and uses the corresponding

SCLK, SDA pins. The ADDR pin is also used to select the CIF1 Device ID.

In 2-wire (I2C) mode, the WM8281 is a slave device on the control interface; SCLK is a clock input,

while SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters)

on the same interface, the WM8281 transmits logic 1 by tri-stating the SDA pin, rather than pulling it

high. An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be

recognised by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 8-bit device ID (this is not the same as the address of each register in the WM8281).

For Control Interface 1, the device ID is selectable using the CIF1ADDR pin, as described in Table

114.

The LSB of the Device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for

“Write”.

The CIF1ADDR logic level is referenced to the DBVDD1 power domain. An internal pull-down resistor

is enabled by default on the CIF1ADDR pin; this can be configured using the ADDR_PD register bit

described in Table 113.

WM8281ECS/R Datenblatt(PDF) 291 Page - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 291 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL