WM8281ECSSLASHR datasheet(292/392 Pages) CIRRUS

292 / 392 page

WM8281

292

Rev 4.0

CIF1ADDR

DEVICE ID (CIF1)

Logic 0

0011 010x = 34h (write) / 35h (read)

Logic 1

0011 011x = 36h (write) / 37h (read)

Table 114 Control Interface Device ID Selection

For Control Interface 2, the device ID is selectable using the I2C2_DEV_ID control register, as

described in Table 113. Note that this register identifies bits [7:1] of the CIF2 I2C device ID; the LSB

of the Device ID is the Read/Write bit, as described above.

Under default register conditions, the CIF2 device ID is 34h (write) / 35h (read).

The WM8281 operates as a slave device only. The controller indicates the start of data transfer with a

high to low transition on SDA while SCLK remains high. This indicates that a device ID, and

subsequent address/data byte(s) will follow. The WM8281 responds to the start condition and shifts in

the next eight bits on SDA (8-bit device ID, including Read/Write bit, MSB first). If the device ID

received matches the device ID of the WM8281, then the WM8281 responds by pulling SDA low on

the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the

WM8281 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8281, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCLK remains high. After receiving a complete address and data sequence the WM8281 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns

to the idle condition.

The WM8281 supports the following read and write operations:



Single write



Single read



Multiple write (with optional auto-increment)



Multiple read (with optional auto-increment)

The sequence of signals associated with a single register write operation is illustrated in Figure 72.

A25

A31

SDA

SCLK

device ID

– A8

A24

A15

Note: The SDA pin is used as input for the control register address and data; SDA is

pulled low by the receiving device to provide the acknowledge (ACK) response

R/W

– A24

– A0

START

(Write)

ACK

A17

A23

A16

– A16

ACK

data bits B15

– B8

B15

data bits B7

– B0

ACK

STOP

Figure 72 Control Interface 2-wire (I2C) Register Write

WM8281ECS/R Datenblatt(PDF) 292 Page - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 292 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL