WM8281ECSSLASHR datasheet(293/392 Pages) CIRRUS

293 / 392 page

WM8281

Rev 4.0

293

The sequence of signals associated with a single register read operation is illustrated in Figure 73.

A25

A31

SDA

SCLK

device ID

A24

Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses

R/W

– A24

START

(Write)

ACK

A17

A23

A16

– A16

device ID

B15

data bits B15

– B8

ACK

R/W

(Read)

data bits B7

– B0

ACK

STOP

ACK

Rpt

START

– A0

– A8

A15

ACK

Figure 73 Control Interface 2-wire (I2C) Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 115.

Note that, for multiple write and multiple read operations, the auto-increment option may be enabled.

The I2C

multiple transfers illustrated below assume that “auto-increment by 1” is selected in each

case. Auto-increment is enabled by default, as noted in Table 113.

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge (SDA Low)

¯¯

Not Acknowledge (SDA High)

Stop Condition

R/W

¯¯

ReadNotWrite

0 = Write

1 = Read

[White field]

Data flow from bus master to WM8281

[Grey field]

Data flow from WM8281 to bus master

Table 115 Control Interface (I2C) Terminology

Device ID

Address Byte [3]

(0)

8 bit Device ID

8 bits

Address Byte [2]

8 bits

Address Byte [1]

8 bits

MSByte Data

LSByte Data

8 bits

Address Byte [0]

(Most Significant Byte)

(Least Significant Byte)

Figure 74 Single Register Write to Specified Address

Device ID

(0)

Device ID

MSByte Data

(1)

LSByte Data

Address Byte [3]

Address Byte [2]

Address Byte [1]

Address Byte [0]

(Most Significant Byte)

(Least Significant Byte)

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