L9660 datasheet(25/49 Pages) STMICROELECTRONICS

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L9660

Functional description

A “real-time” current measurement status of all the channels is available. If a current limit

status request is sent then the L9660 reports in the next SPI transfer whether the current is

above or below IMEAS for each of the channels. The current status results can be read at

any time and correctly reports whether current is flowing. The content of the internal current

status register is captured on the falling edge of chip select during the SPI response. The

internal status register is updated at a nominal sample time of 25 µs and is independent

from SPI transfers.

For this circuit there is a continuously performed compensation of the comparator in order to

remove offset errors, which is independent from SPI commands. The compensation is being

performed every 12.8 µs based on the internal clock.

3.4.3

Fire enable (FEN) function description

The Fire Enable (FEN) function is the result of the FENx input OR’d with the internal FEN

latch. If the FEN latch is not enabled and the FENx pin is low then activations of the FET

drivers are disabled except as indicated during the MOS test. All internal diagnostics are

active, and results are available through the serial interface. This pin must be pulled high to

initiate the FEN latch function (if programmed) and enable firing of the FET drivers.

There are two FEN function blocks



FEN Function 1 is FEN1 input OR’d with FEN1 latch timer and used for enabling

channels 0 & 1



FEN Function 2 is FEN1 input OR’d with FEN2 latch timer and used for enabling

channels 2 & 3

The FEN function is considered active when the pin is active (‘1’ or high) for more than 12

microseconds. Tolerance range for the filter used is 12 to 16 µs.

When the FENx input is active, ‘1’, the FEN function activates. When the FENx input state

transitions from ‘1’ to ‘0’, the programmable latching function holds the FEN function

active until the time-out of the FEN timer. The programmable latch and hold function are

capable of delays of 0ms, 128ms, 256ms, and 512ms. There are 2 independent timers with

the timer for FEN1 associated with channels 0 & 1, timer for FEN2 associated with channels

2 & 3. The timer is reset to the programmed time when the FENx pin transitions from

‘0’ to ‘1’. The programmable counter delay is set through a SPI command.

3.4.4

Squib diagnostics

Overview

The ASIC is able to perform the following diagnostics



Short to battery and ground on both SQHx and SQLx pins with or without a squib



Loop to loop diagnostics



Squib resistance measurement



Squib High resistance



High side safing FET diagnostics



VRESx voltage status



High and low side FET diagnostics

Below is a block diagram showing the components involved in the squib diagnostics.

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