L9660 datasheet(39/49 Pages) STMICROELECTRONICS

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L9660

Functional description

STB/STG bit definition with MOSI D11:D9=111 (HS FET)

STB, STG bits see table below

HSS1:HSS0 bit definition with MOSI D11:D9=011 (High side safing)

HSS1:HSS0 bits

see table below

VR1:VR0 bit definition with MOSI D11:D9=010 (VRESx supply voltage)

VR1:VR0 bits

see table below

HSR Bit Definition with MOSI D11:D9=101 (High Squib Resistance)

HSR bit

Bit used for indicating a high squib resistance.

0 = Squib Resistance below RSQHIZ

1 = Squib Resistance above RSQHIZ

Bits D6

Fault present prior to running LS FET or HS FET test

(diagnostics aborted)

0 = Normal

1 = Test not run - Fault present (FEN in incorrect state, short

to battery or ground)

Bits D5

Bit definition based on diagnostic selection.

FT bit Read Only - Used for LS FET or HS FET diagnostics

and is the status of the FET timer

0 = FET timer not active

1 = FET timer active

Table 22. Diagnostic mode HS FET selection

Condition

STB

STG

Test in Process (FT=1); Fault present prior to run test (FP=1); or HS

FET/VRESx open fault (FP=0,FT=0). Only Valid if test is in process

or inactive.

Test Pass if leakage diagnostics did not indicate a short to battery.

Short to ground occurred during test.

Table 23. Diagnostic mode HSS selection

Condition

HSS1

HSS0

(VSDIAG-VRESx) < VHSSSHORT_th

VHSSSHORT_th < (VSDIAG-VRESx) < VHSSOPEN_th

VHSSOPEN_th < (VSDIAG-VRESx)

Table 24. Diagnostic mode VRESx selection

Condition

VR1

VR0

VRESx < VVRESXLO_th

VVRESXLO_th < VRESx < VVRESXHI_th

VVRESXHI_th < VRESx

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