80960JD datasheet(28/59 Pages) INTEL

28 / 59 page

80960JD

PRODUCT PREVIEW

4.0

ELECTRICAL SPECIFICATIONS

4.1

Absolute Maximum Ratings

Parameter

Maximum Rating

Storage Temperature

–65oC to +150oC

Case Temperature Under Bias

–65oC to +110oC

Supply Voltage wrt.

VSS

–0.5 V to + 4.6 V

Voltage on

VCC5 wrt. VSS

–0.5 V to + 6.5 V

Voltage on Other Pins wrt.

VSS

–0.5 V to VCC + 0.5 V

NOTICE: This document contains information on

products in the design phase of development. Do

not finalize a design with this information. Revised

information will be published when the product

becomes available. Verify with your local Intel

sales office that you have the latest datasheet

before finalizing a design.

WARNING: Stressing the device beyond the

“Absolute Maximum Ratings” may cause perma-

nent damage. These are stress ratings only. Oper-

ation beyond the “Operating Conditions” is not

recommended and extended exposure beyond the

“Operating Conditions” may affect device reli-

ability.

4.2

Operating Conditions

Table 13. 80960JD Operating Conditions

Symbol

Parameter

Min

Max

Units

Notes

VCC

Supply Voltage

3.15

3.45

VCC5

Input Protection Bias

3.15

5.5

(1)

fCLKIN

Input Clock Frequency

80960JD-66

80960JD-50

80960JD-40

33.3

MHz

Operating Case Temperature (PGA

and PQFP)

0100

°C

NOTES:

1. See Section 4.4, VCC5 Pin Requirements (VDIFF) (pg. 23)

4.3

Connection Recommendations

For clean on-chip power distribution, VCC and VSS

pins separately feed the device’s functional units.

Power and ground connections must be made to all

80960JD power and ground pins. On the circuit

board, every VCC pin should connect to a power

plane and every VSS pin should connect to a ground

plane. Place liberal decoupling capacitance near the

80960JD, since the processor can cause transient

power surges.

Pay special attention to the Test Reset (TRST) pin. It

is essential that the JTAG Boundary Scan Test

Access Port (TAP) controller initializes to a known

state whether it will be used or not. If the JTAG

Boundary Scan function will be used, connect a

pulldown resistor between the TRST pin and VSS. If

the JTAG Boundary Scan function will not be used

(even for board-level testing), connect the TRST pin

to VSS. Also, do not connect the TDI, TDO, and TCK

pins if the TAP Controller will not be used.

Pins identified as NC must not be connected in

the system.

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