80960JD datasheet(33/59 Pages) INTEL

33 / 59 page

80960JD

PRODUCT PREVIEW

RELATIVE OUTPUT TIMINGS

TLX

Address Valid to ALE/ALE Inactive

0.5TC - 5

TLXL

ALE/ALE Width

0.5TC - 7

(9)

TLXA

Address Hold from ALE/ALE Inactive

Equal Loading (9)

TDXD

DT/R Valid to DEN Active

Equal Loading (9)

BOUNDARY SCAN TEST SIGNAL TIMINGS

TBSF

TCK Frequency

0.5TF

MHz

TBSCH

TCK High Time

Measured at 1.5 V (1)

TBSCL

TCK Low Time

Measured at 1.5 V (1)

TBSCR

TCK Rise Time

0.8 V to 2.0 V (1)

TBSCF

TCK Fall Time

2.0 V to 0.8 V (1)

TBSIS1

Input Setup to TCK — TDI, TMS

TBSIH1

Input Hold from TCK — TDI, TMS

TBSOV1

TDO Valid Delay

(1,10)

TBSOF1

TDO Float Delay

(1,10)

TBSOV2

All Outputs (Non-Test) Valid Delay

(1,10)

TBSOF2

All Outputs (Non-Test) Float Delay

(1,10)

TBSIS2

Input Setup to TCK — All Inputs

(Non-Test)

4ns

TBSIH2

Input Hold from TCK — All Inputs

(Non-Test)

6ns

Table 16. 80960JD AC Characteristics (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

Notes

NOTES:

See Table 17 on page 28 for note definitions for this table.

80960JD Datenblatt(PDF) 33 Page - Intel Corporation

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