ECT25S40 datasheet(23/46 Pages) E-CMOS

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4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Continuous Read Mode Reset (FFH or FFFFH)

The“Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O” and

“Fast Read Quad I/O” Instructions to provide the highest random Flash memory access rate

with minimum SPI instruction overhead, thus allowing more efficient XIP(execute in place)

with this

device family.The “Continuous Read Mode” bits M7-0 are set by the Dual/Quad I/O

Read Instructions. M5-4 are used to control whether the 8-bit SPI instruction code (BBh or

EBh) is needed or not for the nextinstruction. When M5-4 = (1,0), the next instruction will be

treated the same as the current Dual/Quad I/O Read instruction without needing the 8-bit

instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI instruction

mode, in which all instructions can be accepted. M7-6 and M3-0 are reserved bits for future

use, either 0 or 1 values can be used.See Figure 18, the Continuous Read Mode Reset

instruction (FFh or FFFFh) can be used to set M4= 1, thus the device will release the

Continuous Read Mode and return to normal SPI operation.

To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed.

The inst

ruction is“FFh”.To reset “Continuous Read Mode” during Dual I/O operation,sixteen

clocks are needed to shift in in

struction “FFFFh

Figure 18. Continuous Read Mode Reset Sequence Diagram

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