ECT25S40 datasheet(33/46 Pages) E-CMOS

33 / 46 page

E-CMOS Corp. (www.ecmos.com.tw)

Page 33 of 46

4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Figure 29. 32KB Block Erase Sequence Diagram

64KB Block Erase (D8H)

The 64KB Block

Erase instruction is for erasing the

all

data

the chosen block. A

Write Enable instruction must previously have been executed to set the Write Enable Latch bit.

The 64KB Block Erase instruction is entered by driving /CS low, followed by the instruction

code, and 3-byte address on SI. Any address inside the block is a valid address for the

64KB Block Erase instruction. /CS must be driven low for the entire duration of the sequence.

See Figure 30, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB

Block Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the

eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase

instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle

(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status

Progress(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed.

At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A

64KB Block Erase instruction applied to a block

which is protected by the Block Protect (SEC,

TB, BP2, BP1, BP0) bits (see

Table 6&7) is not executed.

Figure 30. 64KB Block Erase Sequence Diagram

ECT25S40 Datenblatt(PDF) 33 Page - E-CMOS Corporation