AD6652BBC datasheet(44/76 Pages) AD

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AD6652

Rev. 0 | Page 44 of 76

for averaging and decimating the update samples and taking

their square root to f

mode. In place of the request de

ipping level is subtracted, leaving an error term to be proc-

der loop filter. The rest of the loop

s the desired signal level mode. This

vel

recei

aver

e AD6652 to update the

rece

chan

e accurate

coun

the u

chos

hannel 0. Likewise, the hold-off counter of

and

number that corresponds to the number of CLK cycles that will

IC decimated value

the proper pin sync pin

triggers the AGC hold-off counter with a one-shot pulse every

time the pin is written high. Once triggered, the counter counts

a ne

Note

he hold-off

dela

If the user chooses not to use pin sync signals, the user can use

cont

0x12

n written high, performs an immediate start of

date sample. This bit has a one-shot

ristic an

ot need

to respond

w logic hi

being writte

it. Use of the sync now bit

passes the AG hold-off coun

s and performs sync

ctions witho

elay.

ch Pin Sync logic high initiates a new trigger event for the

een reserved for configuring

ind rms samples, as in desired signal level

sired signal level, a desired

be counted ( a known delay) before a new C

is updated. Writing a logic high to

essed by the second-or

operates the same way a

way, the truncation error is calculated and the AGC loop

operates to maintain a constant truncation error level.

Apart from Bit 4 of the AGC control words, the only register

setting changes compared to the desired signal level mode is

that the desired clipping level is stored in the AGC desired le

registers (0x0C, 0x15) instead of the request signal level (as in

desired signal level mode).

SYNCHRONIZATION

In i stances where the AGC output is connected to a Rake

ver, a signal from the Rake receiver can synchronize t

age-and-update section of th

average power for AGC error calculation and loop filtering. This

ext rnal signal synchronizes the AGC changes to the Rake

iver and makes sure that the AGC gain word does not

ge over a symbol period and, therefore, mor

esti ation. The external synchronization signal is connected t

one or more of the pin sync pins (A, B, C, or D).

synchronization requires the use of an AGC hold-off

ter. The hold-off counter of AGC A shares the pin sync th

ser has assigned to DDC processing Channel 0. Therefor

ser must attach the external sync signal to the pin sync

en for DDC C

AGC B shares the pin synch that the user has assigned to DDC

processing Channel 2. Therefore, the user must attach the

external sync signal to the pin sync that will be assigned to

DDC Channel 2.

The hold-off counter register, 0x0B and 0x13 for AGC A

AGC B, respectively, must be programmed with a 16-bit

down to a value of one and then causes a start of decimation for

w update sample.

: Setting the hold-off count to zero disables t

counter. Setting the hold-off count to one provides the smallest

the ync Now command through the microport. Each AGC

rol register has a sync now bit in Registers 0x0A:3 and

:3 that, whe

decimation for a new up

characte

d does n

to be reset in order

to a ne

n to

ter

fun

ut d

hold-off counter unless First Sync Only of the AGC’s control

signal is recognized and any others disregarded until First Sync

Only is reset.

Along with updating a new decimation value, the CIC filter

accumulator can be reset if the Init on Sync bit (Bit 2) of the

AGC control register is set. Init on Sync is triggered by either

sync signal, pin sync, or sync now.

Addresses 0x0A to 0x11 have b

AGC A, and Addresses 0x12 to 0x19 have been reserved for

configuring AGC B. The register specifications are detailed in

Table 29.

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