AD6652BBC datasheet(61/76 Pages) AD

61 / 76 page

AD6652

Rev. 0 | Page 61 of 76

suit

scalar can be chosen. For

ils, see the Second

ection.

1: rCIC2 Interpol

)

s register is used to

ation in the rCIC2 fil

value written to th

inus

C2 interpolation can range from 1 to 512, dependin

pon the decimation o he rCIC2. There is no timing error

ciated with this in

ils, see the Secon

CIC Filter sect

C2 scale regist

is used to provide attenuation to

mpensate for the gai of the rCIC2 and to adjust the linea i-

zation of the data from the floating-point input. The use of this

ale register is influenced by the rCIC2 growth. For details, see

ator,

ate for the

fth-Order CIC

− 1)

nus

el is synchronized,

it retains the phase setting chosen here. This can be used as part

overy loop with an external processor or can

ulti

ile using a single RCF

t Filter section.

The numbe

nus 1 is written to this

er.

0xA3: RCF Coeffici

iste

tion of the 256-word

o select

among mult

to memory and

nced b

iste

inter is updated

(from the shadow register) on every new filter output sample.

This allows the coefficient offset to be written without

with the new filter.

sses the RCF filter and sends the CIC5 output data to

the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5 data

trol

controls the source of the input data to the

processes the output data of its

t processes the data from the

ed to allow multiple RCFs to be used together to

MrCIC2 must be chosen larger than LrCIC2, and both must be

chosen such that a

able rCIC2

deta

-Order RCIC Filter s

0x9

ation − 1 (LrCIC2 − 1

Thi

set the interpol

ter.

The

is register is the interpolation m

The rCI

f t

asso

terpolation. For deta

Order R

ion.

0x92: rCIC2 Scale

The rCI

the Second-Order RCIC Filter section.

Bit 11 is reserved. Write all bits to Logic 0.

Bit 10 is reserved. Write all bits to Logic 0.

Bits 9–5 are the actual scale value used when the level indicato

LI pin associated with this channel, is active (Logic 1).

Bits 4–0 are the actual scale value used when the level indic

LI pin associated with this channel, is inactive (Logic 0).

0x93: Reserved

Eight bits, reserved (must be written low).

0x94: CIC5 Decimation – 1 (MCIC5 − 1)

This register is used to set the decimation in the CIC5 filter. The

8-bit value written to this register is the decimation minus 1.

0x95: CIC5 Scale

The 5-bit CIC5 scale factor is used to compens

growth of the CIC5 filter. For details, see the Fi

Filter section.

0x96: Reserved

Reserved (must be written low).

0x97–0x9F: Unused

Unused.

0xA0: RCF Decimation − 1 (MRCF

This register is used to set the decimation of the RCF stage. Th

value written to this register is the desired decimation mi

one. Although this is an 8-bit register that allows decimation u

to 256, most filter designs should be limited to between 1 an

32. Higher decimations are allowed, but the alias rejection of the

RCF might not be acceptable for some applications.

0xA1: RCF Decimation Phase (PRCF)

This register allows any one of the MRCF phases of the filter to

used and can be adjusted dynamically. Each time a filter is

started, this phase is updated. When a chann

a timing rec

low m

ple RCFs to work together wh

air. For details, see the RAM Coefficien

xA2: RC Number of Tap – 1 (NRCF − 1)

r of taps for the RCF filter mi

gist

ent Offset (CORCF)

his reg

r is used to specify which sec

efficien memory is used for a filter. It can be used t

iple filters that are loaded in

fere

y this pointer.

his reg

r is shadowed, and the filter po

disturbing operation, even while a filter is being computed. Th

next sample that comes out of the RCF is

0xA4: RCF Control Register

The RCF control register is an 11-bit register that controls the

general features of the RCF as well as output formatting. The

bits of this register and their functions are described below.

Bit 10 bypa

can be accessed from this register, if Bit 9 of the output con

Bit 9 of this register

RCF. If this bit is 0, then the RCF

own channel. If this bit is 1, then i

CIC5 of another channel. The CIC5 channels that the RCF c

be connected to when this bit is 1 are shown in the Table 26.

These can be us

process wider bandwidth channels

Table 26. RCF Input Configurations

Channel

RCF Input Source when Bit 9 Is 1

Bit 8 is used as an extra address to allow a second block of

128 words of CMEM to be addressed by the channel addres

at 0x00–0x7F. If this bit is 0, then

ses

the first 128 words are written;

if this bit is 1, then the next 128 words are written. This bit is

hosen. These modes are enabled by

Bits 5 and 4 of this register. When this bit is 0, then the I and Q

output exponents are determined separately based on their

used to program only the coefficient memory so that filters

longer than 128 taps can be realized.

Bit 7 is used to control the output formatting of the AD6652’s

RCF data. This bit is used only when the 8 + 4 or 12 + 4

floating-point modes are c

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