AD6652BBC datasheet(7/76 Pages) AD

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AD6652

Rev. 0 | Page 7 of 76

ELECTRICAL CHARACTERISTICS

AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.

Table 5.

Parameter (Conditions)

Temp

Test Level

Min

Typ

Max

Unit

LOGIC INPUTS

Logic Compatibility

Full

3.3 V CMOS

Logic 1 Voltage

Full

2.0

Logic 0 Voltage

Full

0.8

Logic 1 Current

Full

−10

+10

µA

Logic 0 Current

Full

−10

+10

µA

Input Capacitance

25°C

LOGIC OUTPUTS

Logic Compatibility

Full

3.3 V CMOS/TTL

Logic 1 Voltage (VOH) (IOH = 0.25 mA)

Full

2.4

VDDIO − 0.2

Logic 0 Voltage (VOL) (IOL = 0.25 mA)

Full

0.2

0.4

SUPPLY CURRENTS

Narrow Band (150 kHz BW) (61.44 MHz CLK)

Four Individual Channels

IAVDD

25°C

160

200

215

IVDD

25°C

240

280

300

IVDDIO

25°C

CDMA (1.25MHz BW) (61.44 MHz CLK) Example1

IAVDD

25°C

200

IVDD

25°C

336

IVDDIO

25°C

WCDMA (5 MHz BW) (61.44 MHz CLK) Example1

IAVDD

25°C

200

IVDD

25°C

330

IVDDIO

25°C

TOTAL POWER DISSIPATION

Narrow Band (150 kHz BW) (61.44 MHz CLK)

Four Individual Channels

25°C

1.2

1.5

1.6

CDMA (61.44 MHz)1

25°C

1.7

WCDMA (61.44 MHz)1

25°C

1.7

ADC in Standby and DDC in Sleep Mode2

25°C

2.3

1 All signal processing stages and all DDC channels active.

2 ADC standby power measured with ACLK inactive.

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