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AT25SL128A Datenblatt(PDF) 19 Page - Dialog Semiconductor

Teilenummer AT25SL128A
Bauteilbeschribung  128-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support
PDF  75 Pages
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AT25SL128A Datenblatt(HTML) 19 Page - Dialog Semiconductor

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AT25SL128A
DS-AT25SL128A–109K–02/2019
not set the Write Enable Latch (WEL) bit. Once Write Enable for Volatile Status Register is set, a Write Enable
instruction should not have been issued prior to setting Write Status Register instruction (01h or 31h). When Write
Enable for Volatile Status Register (50h) is set in QPI Mode, the SUS bit (S15) and Reserved bits (S13, S12, S11 and
S10) of the Status Register-2 must be driven to high after Write Status Register instruction(01h).Once Read Status
Register (05h or 31h) is issued the read values of SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the
Status Register-2 are ignored.
Figure 7-2.
Write Enable for Volatile Status Register Instruction for SPI Mode (left) and QPI Mode (right)
7.4
Write Disable (04h)
The Write Disable instruction is to reset the Write Enable Latch (WEL) bit in the Status Register. To enter the Write Disable
instruction, CS goes low prior to the instruction “04h” into Data Input (SI) pin on the rising edge of SCK, and then driving CS
high. WEL bit is automatically reset write- disable status of “0” after Power-up and upon completion of the every Program,
Erase and Write Status Register instructions.
Figure 7-3.
Write Disable Instruction for SPI Mode (left) and QPI Mode (right)



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