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AT25SL128A Datenblatt(PDF) 24 Page - Dialog Semiconductor |
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AT25SL128A Datenblatt(HTML) 24 Page - Dialog Semiconductor |
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24 / 75 page ![]() 24 AT25SL128A DS-AT25SL128A–109K–02/2019 Figure 7-12. Fast Read instruction (QPI Mode, 80MHz) Figure 7-13. Fast Read instruction (QPI Mode, 104MHz) 7.11 Fast Read Dual Output (3Bh) By using two pins (IO0 and IO1, instead of just IO0), The Fast Read Dual Output instruction allows data to be transferred from the AT25SL128A at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for application that cache code-segments to RAM for execution. The Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). After the 24-bit address, this is accomplished by adding eight “dummy” clocks as shown in Figure 7-14. The dummy clocks allow the internal circuits additional time for setting up the initial address. During the dummy clocks, the data value on the SO pin is a “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock. |
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