AT25SL128A datasheet(23/75 Pages) DIALOG

Teilenummer	AT25SL128A

Bauteilbeschribung	128-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	75 Pages

Scroll/Zoom	100%

Hersteller	DIALOG [Dialog Semiconductor]

Direct Link	http://www.dialog-semiconductor.com/

Logo

23 / 75 page

AT25SL128A

DS-AT25SL128A–109K–02/2019

Figure 7-10. Read Data Instruction

7.9

Fast Read (0Bh)

The Fast Read instruction is high speed reading mode that it can operate at the highest possible frequency of FR. The address

is latched on the rising edge of the SCK. After the 24-bit address, this is accomplished by adding “dummy” clocks as shown in

Figure 7-11. The dummy clocks means the internal circuits require time to set up the initial address. During the dummy clocks,

the data value on the SO pin is a “don’t care”. Data of each bit shifts out on the falling edge of SCK.

Figure 7-11. Fast Read Instruction (SPI Mode)

7.10

Fast Read in QPI Mode

When QPI mode is enabled, the number of dummy clock is configured by the “Set Read Parameters (C0h)” instruction to

accommodate wide range applications with different needs for either maximum Fast Read frequency or minimum data

access latency. Depending on the Read Parameter Bit P[4] and P[5] setting, the number of dummy clocks can be

configured as either 4, or 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 4.

(Please refer to Figure 7-12, Figure 7-13 and Figure 7.11).

AT25SL128A Datenblatt(PDF) 23 Page - Dialog Semiconductor