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UPD161622 Datenblatt(PDF) 2 Page - NEC |
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UPD161622 Datenblatt(HTML) 2 Page - NEC |
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2 / 103 page ![]() Data Sheet S15649EJ2V0DS 2 µ PD161622 1. BLOCK DIAGRAM LCD drive circuit Display data RAM (132 x 16 x 176 bits) S1 Decoder Level shifter (2.5 V 5 V) Display data latch Arbiter Internal timing generator Command decoder Address decoder / controller Data register VCOM generator I/O buffer Gate control Gray scale generator LCD timing control BGR Oscillator Calibrator S395 S4 S3 S2 S396 PS control CVPH CVPL CVNH CVNL OSCOUT RSEL OSCIN D/A converter BGRIN DAC0 to DAC7 VCOMR FBRSEL Remark /xxx indicates active low signal. |
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