UPD161622 datasheet(23/103 Pages) NEC

23 / 103 page

Data Sheet S15649EJ2V0DS

µ PD161622

Figure 5

−7. Combination of INC, XDIR, and YDIR, and Address Scanning Image

X address

00H

83H

00H

AFH

X address

00H

83H

00H

AFH

A-1

B-1

B-2

B-3

B-4

A-2

A-3

A-4

5.2.3 Column address circuit

When the contents of the display data RAM are displayed, column addresses are output to the SEG output pins as

shown in Figure 5

−8.

The correspondence relationship between the column addresses of the display RAM and segment outputs can be

reversed by the ADC flag (segment driver direction select flag) of control register 1 (R0) as shown in Table 5

−8. This

reduces the restrictions on chip layout when the LCD module is assembled.

Table 5

−8. Relationship between Column Address of Display RAM and Segment Output

SEG Output

SEG1

SEG2

→

SEG385

SEG386

000H

→

Column address

→

18AH

18BH

ADC

18BH

18AH

←

Column address

←

001H

000H

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