 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
UPD161622 Datenblatt(PDF) 30 Page - NEC |
|
|
|||||||||||||||||||||||||||||
UPD161622 Datenblatt(HTML) 30 Page - NEC |
|
|
30 / 103 page  Data Sheet S15649EJ2V0DS 30 µ PD161622 5.4 Display Timing Generator 5.4.1 Drive timing The µ PD161622 generates the TFT-LCD drive timing inside the µ PD161622. The TFT-LCD panel is driven at the timing of one line selection period generated based on the calibration time (tcal) set by the calibration function, as shown in the figure below. One line selection period is made up of a pre-charge period, a source output period, and the µ PD161622 output control clock. The pre-charge and source output periods are set by the pre-charge period setting register (R46) and calibration register (R45), respectively, based on the following expressions. 1 line selection period = tcal Pre-charge period = tpr Source output period = tsout tcal: Calibration setting time [R45] tpr = (1/fOSC) x (CLKpr + 2 CLK) tsout = tcal - (tpr + 3 CLK) CLKcal: Calibration setting time (tcal) clock number = tcal ÷ (1fOSC) CLKpr: Pre-charge peiod setting register clock number [R46: PLIMn] n 1 CLK = 1/fOSC fOSC: Oscillator frequency |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
