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UPD161623 Datenblatt(PDF) 2 Page - NEC |
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UPD161623 Datenblatt(HTML) 2 Page - NEC |
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2 / 83 page ![]() Data Sheet S15817EJ2V0DS 2 µµµµPD161623 1. BLOCK DIAGRAM LCD drive circuit Display data RAM (176 x 18 x 240 bits) Y1 Decoder Level shifter (2.5 V 5 V) Display data latch RAM controller Internal timing generator Command decoder Address decoder / controller Data register VCOM generator I/O buffer Gate control Gray scale generator LCD timing control BGR Oscillator Calibrator Y527 Y4 Y3 Y2 Y528 PS control CVPH CVPL CVNH CVNL OSCOUT OSCSEL OSCIN D/A converter BGRIN DAC0 to DAC7 VCOMR FBRSEL Remark /xxx indicates active low signal. |
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