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UPD161623 Datenblatt(PDF) 76 Page - NEC |
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UPD161623 Datenblatt(HTML) 76 Page - NEC |
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76 / 83 page ![]() Data Sheet S15817EJ2V0DS 76 µµµµPD161623 When VDD1 = 2.5 to 3.6 V, VDD2 = 2.5 to 3.6 V, VDD2 ≥≥≥≥ VDD1 (high-speed RAM write mode, valid only for writing data, R114 = R115 = 01H) Parameter Symbol Condition MIN. TYP. Note MAX. Unit Address hold time tAH8 RS 0 ns Address setup time tAS8 RS 0 ns System cycle time tCYC8 125 ns Control low-level pulse width (/WR) tCCLW /WR 60 ns Control high-level pulse width (/WR) tCCHW /WR 30 ns Data setup time tDS8 D0 to D17 80 ns Data hold time tDH8 D0 to D17 0ns Note TYP. values are reference values when TA = 25 °C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VDD1. When VDD1 = 1.7 to 2.5 V, VDD2 = 2.5 to 3.6 V, VDD2 ≥≥≥≥ VDD1, (high-speed RAM write mode, valid only for writing data, R114 = R115 = 01H) Parameter Symbol Condition MIN. TYP. Note MAX. Unit Address hold time tAH8 RS 0 ns Address setup time tAS8 RS 0 ns System cycle time tCYC8 167 ns Control low-level pulse width (/WR) tCCLW /WR 60 ns Control high-level pulse width (/WR) tCCHW /WR 50 ns Data setup time tDS8 D0 to D17 100 ns Data hold time tDH8 D0 to D17 0ns Note TYP. values are reference values when TA = 25 °C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VDD1. |
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