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UPD161623 Datenblatt(PDF) 78 Page - NEC

Teilenummer UPD161623
Bauteilbeschribung  528 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM
PDF  83 Pages
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Hersteller  NEC [NEC]
Direct Link  http://www.nec.com/
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Data Sheet S15817EJ2V0DS
78
µµµµPD161623
When VDD1 = 2.5 to 3.6 V, VDD2 = 2.5 to 3.6 V, VDD2
≥≥≥≥ VDD1 (normal mode, R114 = R115 = 01H)
Parameter
Symbol
Condition
MIN.
TYP.
Note
MAX.
Unit
Address hold time
tAH6
RS
0
ns
Address setup time
tAS6
RS
0
ns
System cycle time
tCYC6
250
ns
Data setup time
tDS6
D0 to D17
80
ns
Data hold time
tDH6
D0 to D17
0ns
Access time
tACC6
D0 to D17, CL = 100 pF
110
ns
Output disable time
tOH6
D0 to D17, CL = 100 pF
10
100
ns
Enable high pulse width
Read
tEWHR
E
140
ns
Write
tEWHW
E
120
ns
Enable low pulse width
Read
tEWLR
E80
ns
Write
tEWLW
E60
ns
Note TYP. values are reference values when TA = 25
°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VDD1
.
When VDD1 = 1.7 to 2.5 V, VDD2 = 2.5 to 3.6 V, VDD2
≥≥≥≥ VDD1 (normal mode, R114 = R115 = 01H)
Parameter
Symbol
Condition
MIN.
TYP.
Note
MAX.
Unit
Address hold time
tAH6
RS
0
ns
Address setup time
tAS6
RS
0
ns
System cycle time
tCYC6
333
ns
Data setup time
tDS6
D0 to D17
100
ns
Data hold time
tDH6
D0 to D17
0ns
Access time
tACC6
D0 to D17, CL = 100 pF
150
ns
Output disable time
tOH6
D0 to D17, CL = 100 pF
10
150
ns
Enable high pulse width
Read
tEWHR
E
160
ns
Write
tEWHW
E
160
ns
Enable low pulse width
Read
tEWLR
E
140
ns
Write
tEWLW
E
100
ns
Note TYP. values are reference values when TA = 25
°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VDD1
.



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