LPC47N237-MD datasheet(40/138 Pages) SMSC

40 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

Revision 0.3 (10-26-04)

Page 40

SMSC DS – LPC47N237

DATASHEET

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

(NOTE 8.2

)

HIGH

SPEED BIT

(NOTE 8.3

)

1200

1800

2000

0.005

2400

3600

4800

7200

9600

19200

38400

0.030

57600

0.16

115200

0.16

230400

32770

0.16

460800

32769

0.16

Note 8.2

The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

Note 8.3

The High Speed bit is located in the Device Configuration Space.

Table 8.4 – UART Reset Function Table

RESET CONTROL

RESET STATE

Interrupt Enable Register

RESET

All bits low

Interrupt Identification Reg.

RESET

Bit 0 is high; Bits 1 - 7 low

FIFO Control

RESET

All bits low

Line Control Reg.

RESET

All bits low

MODEM Control Reg.

RESET

All bits low

Line Status Reg.

RESET

All bits low except 5, 6 high

MODEM Status Reg.

RESET

Bits 0 - 3 low; Bits 4 - 7 input

TXD1, TXD2

RESET

High

INTRPT (RCVR errs)

RESET/Read LSR

Low

INTRPT (RCVR Data Ready)

RESET/Read RBR

Low

INTRPT (THRE)

RESET/ReadIIR/Write THR

Low

OUT2B

RESET

High

RTSB

RESET

High

DTRB

RESET

High

OUT1B

RESET

High

RCVR FIFO

RESET/

FCR1*FCR0/_FCR0

All Bits Low

XMIT FIFO

RESET/

FCR1*FCR0/_FCR0

All Bits Low

LPC47N237-MD Datenblatt(PDF) 40 Page - SMSC Corporation

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