LPC47N237-MD datasheet(63/138 Pages) SMSC

63 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC DS – LPC47N237

Page 63

Revision 0.3 (10-26-04)

DATASHEET

Interrupts

The interrupts are enabled by serviceIntr in the ecr register.

serviceIntr = 1

Disables the DMA and all of the service interrupts.

serviceIntr = 0

Enables the selected interrupt condition. If the interrupting condition is valid, then the

interrupt is generated immediately when this bit is changed from a 1 to a 0. This can

occur during Programmed I/O if the number of bytes removed or added from/to the FIFO

does not cross the threshold.

An interrupt is generated when:

For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received.

For Programmed I/O:

a) When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free

bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever

there are writeIntrThreshold or more free bytes in the FIFO.

b) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes

in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there

are readIntrThreshold or more bytes in the FIFO.

When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0

and nFault is asserted.

When ackIntEn is 1 and the nAck signal transitions from a low to a high.

FIFO Operation

The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port

can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO

is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be

addressed separately.)

After a reset, the FIFO is disabled.

Each data byte is transferred by a

Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode.

The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold>

ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to

15.

A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster

servicing of the request for both read and write cases. The host must be very responsive to the service

request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used

with a "sluggish" system by affording a long latency period after a service request, but results in more

frequent service requests.

DMA Transfers

DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA

services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O

case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it

sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by encoding the

nLDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the

terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted,

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