LPC47N237-MD datasheet(41/138 Pages) SMSC

41 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC DS – LPC47N237

Page 41

Revision 0.3 (10-26-04)

DATASHEET

Table 8.5 – Register Summary for an Individual UART Channel

ADDRESS

(Note 8.4)

SYMBOL

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

ADDR = 0

DLAB = 0

Receive Buffer Register (Read Only)

RBR

Data Bit 0

(Note 8.5)

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

ADDR = 0

DLAB = 0

Transmitter Holding Register (Write Only)

THR

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

ADDR = 1

DLAB = 0

Interrupt Enable Register

IER

Enable

Received

Data

Available

Interrupt

(ERDAI)

Enable

Transmitter

Holding

Empty

Interrupt

(ETHREI)

Enable

Receiver

Line Status

Interrupt

(ELSI)

Enable

MODEM

Status

Interrupt

(EMSI)

ADDR = 2

Interrupt Ident. Register (Read Only)

IIR

“0” if Interrupt

Pending

Interrupt ID

Bit

Interrupt ID

Bit

Interrupt ID

Bit

(Note 8.9)

FIFOs

Enabled

(Note 8.9)

FIFOs

Enabled

(Note 8.9)

ADDR = 2

FIFO Control Register (Write Only)

FCR

(Note 8.11)

FIFO Enable

RCVR FIFO

Reset

XMIT FIFO

Reset

DMA Mode

Select

(Note 8.10)

Reserved

RCVR Trigger

LSB

RCVR

Trigger

MSB

ADDR = 3

Line Control Register

LCR

Word Length

Select Bit 0

(WLS0)

Word Length

Select Bit 1

(WLS1)

Number of

Stop Bits

(STB)

Parity

Enable

(PEN)

Even Parity

Select

(EPS)

Stick Parity

Set Break

Divisor

Latch

Access Bit

(DLAB)

ADDR = 4

MODEM Control Register

MCR

Data Terminal

Ready (DTR)

Request to

Send (RTS)

OUT1

(Note 8.7)

OUT2

(Note 8.7)

Loop

ADDR = 5

Line Status Register

LSR

Data Ready

(DR)

Overrun

Error (OE)

Parity Error

(PE)

Framing

Error (FE)

Break

Interrupt

(BI)

Transmitter

Holding

(THRE)

Transmitter

Empty

(TEMT)

(Note 8.6)

Error in

RCVR

FIFO

(Note 8.9)

ADDR = 6

MODEM Status Register

MSR

Delta Clear to

Send (DCTS)

Delta Data

Set Ready

(DDSR)

Trailing

Edge Ring

Indicator

(TERI)

Delta Data

Carrier

Detect

(DDCD)

Clear to

Send (CTS)

Data Set

Ready

(DSR)

Ring Indicator

(RI)

Data

Carrier

Detect

(DCD)

ADDR = 7

Scratch Register (Note 5)

SCR

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

ADDR = 0

DLAB = 1

Divisor Latch (LS)

DDL

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

ADDR = 1

DLAB = 1

Divisor Latch (MS)

DLM

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

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