LPC47N237-MD datasheet(79/138 Pages) SMSC

79 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC DS – LPC47N237

Page 79

Revision 0.3 (10-26-04)

DATASHEET

Chapter 15 SMBus GPIO Block

The SMBus GPIO block is a standalone block and consists into two blocks:

−

SMBus Slave Controller

−

SMBus Controlled GPIO Block

The SMBus GPIOs will be accessed via the SMBus interface. There will be no LPC Host access to

the GPIOs in the SMBus GPIO Block.

The SMBus controller and the GPIO block is powered by VTR.

SMBus Isolation Circuitry controls the connection of up to two devices to the SMBus. Two pairs of SMBus

pins (SCLK_1/SDAT_1, SCLK_2/SDAT_2) are individually software selectable to connect internally to the

SCLK and SDAT pins.

See the sub sections below for description on SMBus Slave Controller and the SMBus Controlled GPIO

Block.

15.1

SMBus Slave Controller

The host processor communicates with the LPC47N237 through a series of read/write registers via the

SMBus interface. SMBus is a serial communication protocol between a computer host and its peripheral

devices.

The default power on SMBus address is 010010x binary, where x reflects the state defined by the SMB_A0

pin.

The LPC47N237 SMBus implementation is a subset of the SMBus interface to the host. The SMBus

Controller Block is a slave-only SMBus device. The implementation in the LPC47N237 is a subset of

SMBus since it only supports two protocols.

The Read Byte and Write Byte protocols are the only valid SMBus protocols for the LPC47N237. The part

responds to other protocols as described in the “Invalid Protocol Response Behavior” Section. Reference

the System Management Bus Specification, Rev 1.1.

The SMBus interface is used to read and write the registers in the LPC47N237. The only valid registers for

a read or write protocol are the registers shown in the “SMBus GPIO Register”.

15.1.1 SMBus Pins

Table 15.1 shows the SMBus pins.

LPC47N237-MD Datenblatt(PDF) 79 Page - SMSC Corporation