AT25QL128A datasheet(41/84 Pages) DIALOG

Teilenummer	AT25QL128A

Bauteilbeschribung	1.7 V Minimum, 128-Mbit SPI Serial Flash Memory with Dual I/O, Quad I/O, and QPI Support

PDF	84 Pages

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AT25QL128A

DS-AT25QL128A–129E–01-2021

8.18 32 kbytes Block Erase (52h)

The Block Erase instruction is to erase the data of the selected block as being 1. The instruction is used for

32 kbytes Block erase operation. A Write Enable instruction must be issued before the Block Erase Instruction.

The instruction is initiated by driving the CS pin low and shifting the instruction code 52h followed a 24-bit block

address (A23-A0). (See Figure 8-28 and Figure 8-29.) The CS pin must go high after the eighth bit of the last byte

has been latched in, otherwise, the Block Erase instruction is not executed. After CS is driven high, the self-timed

Block Erase instruction is active for a time duration of tBE1 (see Section 9.6, AC Electrical Characteristics, on page

73).

While the Block Erase cycle is in progress, the Read Status Register instruction can still be read the status of

the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch

(WEL) bit in the Status Register is cleared to 0.

Figure 8-28. 32 kbytes Block Erase Instruction (SPI Mode)

Figure 8-29. 32 kbytes Block Erase Instruction (QPI Mode)

AT25QL128A Datenblatt(PDF) 41 Page - Dialog Semiconductor