AT25SF321 datasheet(7/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

Device Operation

The AT25SF321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI

Master. The SPI Master communicates with the AT25SF321 via the SPI bus which is comprised of four signal lines: Chip

Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the

SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF321

supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the

polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any

data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge

of SCK.

Figure 4-1. SPI Mode 0 and 3

4.1

Dual Output Read

The AT25SF321 features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every

clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of

data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

4.2

Quad Output Read

The AT25SF321 features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every

clock cycle to improve throughput. To accomplish this, the SI, SO, WP, HOLD pins are utilized as outputs for the transfer

of data bytes. With the Quad-Output Read Array command, the SI, WP, HOLD pins become outputs along with the SO

pin.

Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,

the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent

information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and

data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT25SF321 will be ignored by the device and no operation will be started. The device will

continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and

then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the

device, then no operation will be performed and the device will simply return to the idle state and wait for the next

operation.

Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.

Since the upper address limit of the AT25SF321 memory array is 3FFFFFh, address bits A23-A22 are always ignored by

the device.

SCK

MSB

LSB

MSB

LSB

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