AT25SF321 datasheet(21/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

Protection Commands and Features

8.1

Write Enable (06h)

The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state.

The WEL bit must be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security Register

Pages or Write Status Register command can be executed. This makes the issuance of these commands a two step

process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the

Status Register is not set prior to the issuance of one of these commands, then the command will not be executed.

To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the

device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.

When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must

be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary

(multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change.

Figure 8-1. Write Enable

8.2

Write Disable (04h)

The Write Disable command is us0d to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0”

state. With the WEL bit reset, all Byte/Page Program, Erase, Program Security Register Page, and Write Status Register

commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the

WEL bit section of the Status Register description.

To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the

device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.

When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode

must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte

boundary (multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change.

Figure 8-2. Write Disable

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