AT25SF321 datasheet(12/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

Figure 6-5. Dual-I/O Read Array (Previous command set M5, M4 = 1,0)

6.4

Quad-Output Read Array (6Bh)

The Quad-Output Read Array command is similar to the Dual-Output Read Array command. The Quad-Output Read

Array command allows four bits of data to be clocked out of the device on every clock cycle, rather than just one or two.

The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-Output Read Array instruction.

The Quad-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To

perform the Quad-Output Read Array operation, the CS pin must first be asserted and then the opcode 6Bh must be

clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the

location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must

also be clocked into the device.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being

output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O3

pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5, and 4 of the same

data byte will be output on the I/O2, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the

first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively.

The sequence continues with each byte of data being output after every two clock cycles. When the last byte (3FFFFFh)

of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No

delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS

pin will terminate the read operation and put the WP, HOLD, SO, SI pins into a high-impedance state. The CS pin can be

deasserted at any time and does not require that a full byte of data be read.

I/O0

(SI)

SCK

I/O1

(SO)

MSB

410 11

812

15 16

13 14

A22 A20 A18 A16

A0 M6 M4

A14 A

Address Bits

A23-A16

Address Bits

A15-A8

A7-A0

M7-M0

MSB

A23 A21 A19 A17

A1 M7 M5

A15 A

19 20

D6 D4

Byte 1

D7 D5

Byte 2

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