AT25SF321 datasheet(13/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

Figure 6-6. Quad-Output Read Array

6.5

Quad-I/O Read Array(EBh)

The Quad-I/O Read Array command is similar to the Quad-Output Read Array command. The Quad-I/O Read Array

command allows four bits of address to be clocked into the device on every clock cycle, rather than just one.

The Quad-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To

perform the Quad-I/O Read Array operation, the CS pin must first be asserted and then the opcode EBh must be clocked

into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location

of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be

clocked into the device.

After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles will

result in data being output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always

output on the I/O3 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5,

and 4 of the same data byte will be output on the I/O2, I/O1 and I/O0 pins, respectively. During the next clock cycle, bits 3,

2, 1, and 0 of the first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence continues

with each byte of data being output after every two clock cycles.

When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of

the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the

array.Deasserting the CS pin will terminate the read operation and put the I/O3, I/O2, I/O1 and I/O0 pins into a high-

impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.The

Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-I/O Read Array instruction.

I/O0

(SI)

SCK

01101011

410 11

812

42 43

37 38

31 32

29 30

47 48

Opcode

AAAA

AAA

XXXXXXXX

Address Bits A23-A0

Don't Care

Byte 1

OUT

Byte 2

OUT

Byte 3

OUT

Byte 4

OUT

Byte 5

OUT

I/O1

(SO)

High-impedance

D5 D1 D5 D1 D5 D1 D5 D1 D5 D1

I/O2

(WP)

High-impedance

D6 D2 D6 D2 D6 D2 D6 D2 D6 D2

I/O3

(HOLD)

MSB

High-impedance

D7 D3 D7 D3 D7 D3 D7 D3 D7 D3

D4 D0 D4 D0 D4 D0 D4 D0 D4 D0

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