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AT25SL321 Datenblatt(PDF) 56 Page - Dialog Semiconductor

Teilenummer AT25SL321
Bauteilbeschribung  32-Mbit, 1.7 V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support
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AT25SL321
DS-25SL321–112H–2020-10
8.35 Enable Reset (66h) and Reset (99h)
Because of the small package and the limitation on the number of pins, the AT25SL321 provides a software reset
instruction instead of a dedicated RESET pin.
Once the Reset instruction is accepted, any on-going internal operations are terminated and the device returns to
its default power-on state and loses all the current volatile settings, such as Volatile Status Register bits, Write
Enable Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting, Read parameter
setting and Wrap bit setting.
The Enable Reset (66h) and Reset (99h) instructions can be issued in either SPI mode or QPI mode. To avoid
accidental reset, both instructions must be issued in sequence. Any instruction other than Reset (99h) after the
Enable (66h) instruction disables the Reset Enable state. A new sequence of Enable Reset (66h) and Reset (99h)
is needed to reset the device. Once the Reset instruction is accepted by the device takes approximately tRST =
30
μs to reset. During this period, no instructions are accepted.
Data corruption can happen if there is an on-going or suspended internal Erase or Program operation when Reset
instruction sequence is accepted by device. It is recommended to check the BUSY bit and the SUS bit in Status
Register before issuing the Reset instruction sequence.
Figure 8-56. Enable Reset and Reset Instruction (SPI Mode)
Figure 8-57. Enable Reset and Reset Instruction (QPI Mode)



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