AT25SL321 datasheet(8/82 Pages) DIALOG

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AT25SL321

DS-25SL321–112H–2020-10

HOLD

(I/O3)

HOLD

The HOLD pin is used to pause a serial sequence of the SPI flash memory without resetting

the clocking sequence. To enable the HOLD mode, the CS must be in low state. The HOLD

mode effects on with the falling edge of the HOLD signal with CLK being low. The HOLD

mode ends on the rising edge of HOLD signal with SCK being low.

In other words, HOLD mode can't be entered unless SCK is low at the falling edge of the

HOLD signal. And HOLD mode can't be exited unless SCK is low at the rising edge of the

HOLD signal.

If CS is driven high during a HOLD condition, it resets the internal logic of the device. As long

as HOLD signal is low, the memory remains in the HOLD condition. To re-work

communication with the device, HOLD must go high, and CS must go low. See

Figure 9.11

for HOLD timing.

Input/Output

VCC

DEVICE POWER SUPPLY: VCC is the supply voltage. It is the single voltage used for all

device functions including read, program, and erase. The VCC pin is used to supply the

source voltage to the device. Operations at invalid VCC voltages produce spurious results; do

not attempt them.

Power

GND

GROUND:

VSS is the reference for the VCC supply voltage. The ground reference for the

power supply. Connect GND to the system ground.

Power

Table 2-1.

Pin Descriptions (continued)

Symbol

Name and Function

Asserted

State

Type

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