PCIMX6S1CVM08AB datasheet(31/169 Pages) NXP

31 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018

NXP Semiconductors

STOP_ON

• Arm LDO set to 0.9V

• SoC and PU LDOs set to 1.225 V

• HIGH LDO set to 2.5 V

• PLLs disabled

• DDR is in self refresh.

VDD_ARM_IN (1.4V)

VDD_SOC_IN (1.4V)

VDD_HIGH_IN (3.0V)

8.5

Total

61.9

STOP_OFF

• Arm LDO set to 0.9V

• SoC LDO set to: 1.225 V

• PU LDO is power gated

• HIGH LDO set to 2.5 V

• PLLs disabled

• DDR is in self refresh

VDD_ARM_IN (1.4V)

VDD_SOC_IN (1.4V)

13.5

VDD_HIGH_IN (3.0V)

7.5

Total

STANDBY

• Arm and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5V

• PLLs are disabled

• Low Voltage

• Well Bias ON

• Crystal oscillator is enabled

VDD_ARM_IN (0.9V)

0.1

VDD_SOC_IN (0.9V)

VDD_HIGH_IN (3.0V)

Total

19.6

Deep Sleep Mode

(DSM)

• Arm and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5V

• PLLs are disabled

• Low Voltage

• Well Bias ON

• Crystal oscillator and bandgap are disabled

VDD_ARM_IN (0.9V)

0.1

VDD_SOC_IN (0.9V)

VDD_HIGH_IN (3.0V)

0.5

Total

3.4

SNVS only

• VDD_SNVS_IN powered

• All other supplies off

• SRTC running

VDD_SNVS_IN (2.8V)

μA

Total

115

1 The typical values shown here are for information only and are not guaranteed. These values are average values measured

on a typical wafer at 25°C.

Table 11. Stop Mode Current and Power Consumption (continued)

Mode

Test Conditions

Supply

Typical1

Units

PCIMX6S1CVM08AB Datenblatt(PDF) 31 Page - NXP Semiconductors

PCIMX6S1CVM08AB Datenblatt(HTML) 31 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL