PCIMX6S1CVM08AB datasheet(100/169 Pages) NXP

100 / 169 page

i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018

100

NXP Semiconductors

Electrical Characteristics

The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved

relative to the local start point. The data bus of the synchronous interface is output direction only.

4.11.10.6.2 LCD Interface Functional Description

Figure 63 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,

signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

•

DI_CLK internal DI clock is used for calculation of other controls.

•

IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).

In active mode, IPP_DISP_CLK runs continuously.

•

HSYNC causes the panel to start a new line. (Usually IPUx_DIx_PIN02 is used as HSYNC.)

•

VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPUx_DIx_PIN03 is used as VSYNC.)

•

DRDY acts like an output enable signal to the CRT display. This output enables the data to be

shifted onto the display. When disabled, the data is invalid and the trace is off.

(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

Figure 63. Interface Timing Diagram for TFT (Active Matrix) Panels

4.11.10.6.3 TFT Panel Sync Pulse Timing Diagrams

Figure 64 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All the parameters shown in the figure are programmable. All controls are started by

m-1

HSYNC

VSYNC

HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1

LINE n

DRDY

IPP_DISP_CLK

IPP_DATA

PCIMX6S1CVM08AB Datenblatt(PDF) 100 Page - NXP Semiconductors