Preliminary Electrical Characteristics

Preliminary

Freescale Semiconductor

21

5.6

Oscillator and PLL Electrical Characteristics

5.7

External Interface Timing Characteristics

Table 10 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and

output delay with respect to the rising edge of a reference clock. The

reference clock is the FB_CLK output.

All other timing relationships can be derived from these values. Timings

listed in Table 10 are shown in Figure 11 and Figure 12.

Table 9. PLL Electrical Characteristics

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

1

PLL Reference Frequency Range

Crystal reference

External reference

TBD

TBD

16

16

MHz

MHz

2

Core frequency

NOTES:

1

All internal registers retain data at 0 Hz.

TBD

TBD

240

80

MHz

MHz

3

2

This parameter is guaranteed by characterization before qualification rather than 100% tested.

3

Proper PC board layout procedures must be followed to achieve specifications.

—10

ms

4

EXTAL Input High Voltage

All other modes (External, Limp)

4

This parameter is guaranteed by design rather than 100% tested.

TBD

TBD

TBD

TBD

V

V

5

EXTAL Input Low Voltage

Crystal Mode4

All other modes (External, Limp)

TBD

TBD

TBD

TBD

V

V

6

XTAL Load Capacitance2

530

pF

7

PLL Lock Time 2, 5

5

This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in

the synthesizer control register (SYNCR).

—1

ms

8

Duty Cycle of reference 2

40

60

%