MCF5373CAB180 datasheet(32/42 Pages) FREESCALE

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MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

5.13 I2C Input/Output Timing Specifications

Table 16 lists specifications for the I2C input timing parameters shown in Figure 21.

Table 17 lists specifications for the I2C output timing parameters shown in Figure 21.

SSI_BCK rising edge to SSI_MCLK edge

—

SSI_MCLK edge to SSI_BCLK rising edge

—

SSI_TXD/SSI_RXD data set-up time

—

SSI_TXD/SSI_RXD data hold time

—

NOTES:

1fs is the sampling frequency. SSI_BCLK can be operated upto 512 times the sampling frequency to a max frequency of 49.152MHz

Table 16. I2C Input Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

Start condition hold time

—

tcyc

Clock low period

—

tcyc

I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)

—

Data hold time

—

I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V)

—

Clock high time

—

tcyc

Data setup time

—

Start condition setup time (for repeated start condition only)

—

tcyc

Stop condition setup time

—

tcyc

Table 17. I2C Output Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

I11

Start condition hold time

—

tcyc

I2 1

Clock low period

—

tcyc

I3 2

I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)

—

µs

I4 1

Data hold time

—

tcyc

I5 3

I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)

—

I6 1

Clock high time

—

tcyc

I7 1

Data setup time

—

tcyc

I8 1

Start condition setup time (for repeated start condition only)

—

tcyc

I9 1

Stop condition setup time

—

tcyc

Table 15. SSI Timing (continued)

Num

Description

1.8 +/- 0.10V

Unit

Minimum

Maximum

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