Preliminary

Mechanicals and Pinouts

Freescale Semiconductor

8

4

Mechanicals and Pinouts

This section contains drawings showing the pinout and the packaging and mechanical characteristics of

the MCF537x devices.

NOTE

The mechanical drawings are the latest revisions at the time of publication

of this document. The most up-to-date mechanical drawings can be found at

the product summary page located at http://www.freescale.com/coldfire.

USBOTG_VDD

—

—

—

—

H12

VSS

—

—

—

10, 42, 68, 82,

89, 104, 122,

138, 159

G6–G9, H6–H9

PLL_VSS

—

—

—

98

H11

USBHOST_VSS

—

—

—

—

J14

NOTES:

1

Refers to pin’s primary function.

2

Pull-up enabled internally on this signal for this mode.

3

Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by

negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

4

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the

alternate functions.

5

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for

assigning these pins.

6

Pull-down enabled internally on this signal for this mode.

Table 3. MCF5372/3 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1

Alternate 2

MCF5372

MCF5373

160 QFP

MCF5372L

MCF5373L

196 MAPBGA