AD6654SLASHPCB datasheet(70/88 Pages) AD

70 / 88 page

AD6654

Rev. 0 | Page 70 of 88

MICROPORT

The microport on the AD6654 can be used for programming

the part, reading register values, and reading output data (I, Q,

and RSSI words).

Note that, at any given point in time, either the microport or the

serial port can be active, but not both. Some of the balls on the

package are shared between the microport and the serial port

and have dual functionality based on the SMODE pin. The

microport is selected by pulling the SMODE pin low (ground).

Both read and write operations can be performed using the

microport. The direct addressing scheme is used and any

internal register can be accessed using an 8-bit address. The

data bus can be either 8-bit or 16-bit as set by the chip I/O

access control register. Microport operation is synchronous to

CPUCLK, which must be supplied external to the AD6654 part.

CPUCLK should be less than CLK and 100 MHz.

The microport can operate in Intel mode (separate read and

write strobes) or in Motorola mode (single read/write strobe).

The MODE pin is used to select between Intel (INM, MODE =

0) and Motorola (MNM, MODE = 1) modes. Some AD6654

pins have dual functionality based on the MODE pin. Table 27

lists the pin functions for both modes.

Table 27. Microport Programming Pins

Pin Name

Intel Mode

Motorola Mode

RESET

SMODE

Logic 0

MODE

Logic 0

Logic 1

A[7:0]

D[15:0]

R/W (WR)

R/W

DS (RD)

DTACK (RDY)

RDY

DTACK

INTEL (INM) MODE

The programming port performs synchronous Intel-style reads

and writes on the positive edge of the CPUCLK input when

RESET is inactive (active low signal). The CPUCLK pin is

driven by the programming device (CPUCLK of DSP or

FPGA). During a write access, the A[7:0] address bus provides

the address for access, and the D[15:0] bus (D[7:0] if the 8-bit

data bus is used) is driven by the programming device. The data

bus is driven by the AD6654 during a read operation. Intel

mode uses separate read (RD) and write (WR) active low data

strobes to indicate both the type of access and the valid data for

that access.

The chip select (CS) is an active-low input that signals when an

access is active on its programming port pins. During an access,

the AD6654 drives RDY low to indicate that it is performing the

access. When the internal read or write access is complete, the

RDY pin is pulled high. Because the RDY pin is an open-drain

output with a weak internal pull-up resistor (70 kΩ), an

external pull-up resistor is recommended (see the DDC Design

Notes section). Figure 10 and Figure 11 are the timing diagrams

for read and write cycles using the microport in INM mode.

For an asynchronous write operation in Intel (INM) mode, the

CPUCLK should be running. Set up the data and address buses.

Pull the WR signal low and then pull the CS signal low. The

RDY goes low to indicate that the access is taking place inter-

nally. When RDY goes high, the write cycle is complete and CS

can be pulled high to disable the microport.

For an asynchronous read operation on the Intel mode micro-

port, set up the address bus and three-state the data bus. Pull

the RD signal low and then pull the CS signal low. The RDY

goes low to indicate an internal access. When RDY goes low,

valid data is available on the data bus for read.

MOTOROLA (MNM) MODE

The programming port performs synchronous Motorola-style

reads and writes on the positive edge of CPUCLK when RESET

is inactive (active low signal). The A[7:0] bus provides the

address to access and the D[15:0] bus (D[7:0], if the 8-bit data

bus is used) is externally driven with data during a write (driven

by the AD6654 during a read). Motorola mode uses the R/W

line to indicate the type of access (Logic 1 = read, Logic 0 =

write), and the active low data strobe (DS) signal is used to

indicate valid data.

The chip select (CS) is an active-low input that signals when an

access is active on its programming port pins. When the read/

write cycle is complete, the AD6654 drives DTACK low. The

DTACK signal goes high again after either the CS or DS signal

is driven high. Because the DTACK pin is an open-drain output

with a weak internal pull-up resistor (70 kΩ), an external pull-

up resistor is recommended (see the DDC Design Notes

section). Figure 12 and Figure 13 are the timing diagrams for

read and write cycles using the microport in MNM mode.

For an asynchronous write operation on the Motorola mode

microport, the CPUCLK should be running. Set up the data and

address buses. Pull the R/W and DS signals low and then pull

the CS signal low. The DTACK goes low after a few clock cycles

to indicate that the write access is complete and that CS can be

pulled high to disable the microport. For an asynchronous read

operation on the Motorola mode microport, set up the address

bus and three-state the data bus. Pull the RD signal low and

then pull the CS signal low. The DTACK goes low after a few

clock cycles to indicate that valid data is on the data bus.

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