AD6654SLASHPCB datasheet(75/88 Pages) AD

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AD6654

Rev. 0 | Page 75 of 88

<2>: Enable Synchronization from SYNC2 Bit. Similar to

Bit <3> for the SYNC2 pin.

<1>: Enable Synchronization from SYNC1 Bit. Similar to

Bit <3> for the SYNC1 pin.

<0>: Enable Synchronization from SYNC0 Bit. Similar to

Bit <3> for the SYNC0 pin.

Soft Synchronization Configuration <7:0>

<7>: Soft Hop Synchronization Enable Bit. When this bit is set,

hop synchronization is enabled for all channels selected using

Bit 5 through Bit 0. When this bit is cleared, hop synchroniza-

tion is not performed for any channels selected using Bit 5 to

Bit 0.

<6>: Soft Start Synchronization Enable Bit. When this bit is set,

start synchronization is enabled for all channels selected using

Bit 5 through Bit 0. When this bit is cleared, start synchronization

is not performed for any channels selected using Bit 5 to Bit 0.

Bits <5:0> form the SOFT_SYNC control bits. These bits can be

written to by the controller to initiate the synchronization of a

selected channel.

<5>: Soft Sync Channel 5 Enable Bit. When this bit is set, it

enables Channel 5 to receive a hop sync or start sync, as defined

by Bit 7 and Bit 6, respectively. When cleared, Channel 5 does

not receive any soft sync.

<4>: Soft Sync Channel 4 Enable Bit. Similar to Bit <5> for

Channel 4.

<3>: Soft Sync Channel 3 Enable Bit. Similar to Bit <5> for

Channel 3.

<2>: Soft Sync Channel 2 Enable Bit. Similar to Bit <5> for

Channel 2.

<1>: Soft Sync Channel 1 Enable Bit. Similar to Bit <5> for

Channel 1.

<0>: Soft Sync Channel 0 Enable Bit. Similar to Bit <5> for

Channel 0.

<10:0>: Reserved.

<10:9>: Reserved. This bit must be written with Logic 1.

<8:0>: Reserved. This bit must be written with Logic 0.

Interrupt Status Register <15:0>

This register is read only.

<15>: AGC5 RSSI Update Interrupt Bit. If the AGC5 update

interrupt enable bit is set, this bit is set by the AD6654

whenever AGC5 updates a new RSSI word (the new word

should be different from the previous word). If the AGC5

update interrupt enable bit is cleared, then this bit is not set (not

updated). An interrupt is not generated in this case.

Note: For Bits <15:10>, no interrupt is generated, if the new

RSSI word is the same as the previous RSSI word.

<14>: AGC4 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC4.

<13>: AGC3 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC3.

<12>: AGC2 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC2.

<11>: AGC1 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC1.

<10>: AGC0 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC0.

<9>: Channel 5 Data Ready Interrupt Bit. This bit is set to

Logic 1 whenever the channel BIST signature registers are

loaded with data. The conditions required for setting this bit are

that the channel BIST signature registers are programmed for

BIST signature generation and the Channel 5 data ready enable

bit in the interrupt enable register is cleared. If the Channel 5

data ready enable bit in the interrupt enable register is set, the

AD6654 does not set this bit on signature generation and an

interrupt is not generated.

<8>: Channel 4 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 4.

<7>: Channel 3 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 3.

<6>: Channel 2 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 2.

<5>: Channel 1 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 1.

<4>: Channel 0 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 0.

<3>: Reserved. This bit must be written with Logic 0.

<2>: ADC Port Power Monitoring Interrupt Bit. This bit is set

by the AD6654 whenever the ADC port power monitor

interrupt enable bit is set and the ADC port power monitor

timer runs out (end of the ADC port power monitor period). If

the ADC port power monitor interrupt enable bit is cleared, the

AD6654 does not set this bit and does not generate an interrupt.

<1>: Reserved. This bit must be written with Logic 0.

<0>: Reserved. This bit must be written with Logic 0.

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