AD6654SLASHPCB datasheet(85/88 Pages) AD

85 / 88 page

AD6654

Rev. 0 | Page 85 of 88

DDC DESIGN NOTES

The following guidelines describe circuit connections, layout

requirements, and programming procedures for the AD6654.

The designer should review these guidelines before starting the

system design and layout.

• The AD6654 requires the following power-up sequence.

The VDDCORE (1.8 V) is required to settle into nominal

voltage levels before the VDDIO attains the minimum.

• The DDC input clock (CLK) and input (EXP) pins EXP[2:0]

are not 5 V tolerant. Care should be taken to drive these

pins within the limits of VDDIO (3.0 V to 3.6 V). This is

easily accomplished by using the ADC data ready (DR)

output to drive the DDC clock (CLK) input.

• The number format used in this part is twos complement.

All input ports and output ports use twos complement data

format. The formats for individual internal registers are

given in the memory map description of these registers.

• In both microport and serial port operation, the DTACK

(RDY, SDO) and IRP pins are open-drain outputs and

should be terminated externally to VDDIO through a 1 kΩ

pull-up resistor.

DTACK (RDY, SDO)

AD6654

Ω

3.3V

Ω

3.3V

IRP

Figure 75. DTACK, SDO, IRP Pull-Up Resistor Circuit

• A simple RC circuit is used on the EXT_FILTER pin to

balance the internal RC circuit on this pin and maintain a

good PLL clock lock. The recommended circuit is given in

Figure 76. It is further recommended that this RC circuit be

placed as close as possible to the AD6654 part. This layout

consideration ensures that the PLL clock is clean and the

PLL lock is closely maintained.

EXT_FILTER

AD6654

250

Ω

VDD CORE

0.01

µF

Figure 76. EXT_FILTER Circuit for PLL Clock

• By default, the PLL CLK is disabled. It can be enabled by

programming the PLL multiplier and divider bits in the

ADC CLK control register. When the PLL CLK is enabled

by programming this register, it takes about 50 µs to 200 µs

to settle down. While the PLL loop settles down, the voltage

at the EXT_FILTER pin increases from 0 V to VDDCORE

(1.8 V) and settles there. Channel registers and output port

registers (Address 0x68 to Address 0xE7) should not be pro-

grammed before the PLL loop settles down.

• To reset the AD6654, the user must provide a minimum

pulse of 30 ns to the RESET pin. The RESET pin should be

connected to GND (or pulled low) during power-up of the

part. The RESET pin can be pulled high after the power

supplies have settled to nominal values (1.8 V and

3.3 V). At this point, a pulse (pull low and high again)

should be provided to give a reset to the part.

• The CPUCLK (SCLK) is the clock used for programming

via the microport (serial port). This clock needs to be

provided by the designer to the part (slave clock). The

designer should ensure that this clock’s frequency is less

than or equal to the frequency of the CLK signal. Addi-

tionally, the frequency of the CPUCLK (SCLK) should

always be less than 100 MHz.

• The microport data bus is 16 bits wide. Both 8-bit and

16-bit modes are available using this part. If 8-bit mode is

used, the MSB of the data bus (D[15:8]) can be left floating

or connected to GND.

• The output parallel port has a 1-clock cycle overhead. If two

channels (with the same data rates) are output on one

output port in 16-bit interleaved I/Q mode along with an

AGC word, this requires three clock cycles for one sample

from each channel (one clock each for I data, Q data, and

gain data). Therefore, the total number of clock cycles

required to output the data is 3 clocks/channel × 2 channels

+ 1 (overhead) = 7 clock cycles. The number of clock cycles

required for each channel can be 3 (interleaved I + Q + gain

word), or 2 (parallel I /Q + gain) or 2 (interleaved I + Q) or

1 (interleaved I/Q). Designers should make sure that suffi-

cient time is allowed to output these channels on one output

port. Also note that the I, Q, and gain for a particular

channel come out on a single output port and cannot be

divided among output ports.

• When CRCF and DRCF filters are disabled, the coefficient

memory cannot be read back, because the clock to the

coefficient RAM is also cut off.

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