MCP3910 datasheet(23/90 Pages) MICROCHIP

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DS20005116D-page 23

MCP3910

4.0

TERMINOLOGY AND

FORMULAS

This section defines the terms and formulas used

throughout this data sheet. The following terms are

defined:

• MCLK – Master Clock

• AMCLK – Analog Master Clock

• DMCLK – Digital Master Clock

• DRCLK – Data Rate Clock

• OSR – Oversampling Ratio

• Offset Error

• Gain Error

• Integral Nonlinearity Error

• Signal-to-Noise Ratio (SNR)

• Signal-to-Noise Ratio and Distortion (SINAD)

• Total Harmonic Distortion (THD)

• Spurious-Free Dynamic Range (SFDR)

• MCP3910 Delta-Sigma Architecture

• Idle Tones

• Dithering

• Crosstalk

• PSRR

• CMRR

• ADC Reset Mode

• Hard Reset Mode (RESET = 0)

• ADC Shutdown Mode

• Full Shutdown Mode

4.1

MCLK – Master Clock

This is the fastest clock present on the device. This is

the frequency of the crystal placed at the OSC1/OSC2

inputs when CLKEXT = 0 or the frequency of the clock

input at the OSC1/CLKI when CLKEXT = 1. In the

Two-Wire mode, this is the frequency present at the

SCK input pin. See Figure 4-1.

4.2

AMCLK – Analog Master Clock

AMCLK is the clock frequency that is present on the

analog portion of the device, after prescaling has

occurred via the CONFIG0 PRE[1:0] register bits (see

Equation 4-1). The analog portion includes the PGAs

and the two Delta-Sigma modulators.

EQUATION 4-1:

FIGURE 4-1:

Clock Sub-Circuitry.

TABLE 4-1:

MCP3910 OVERSAMPLING

RATIO SETTINGS

CONFIG0

Analog Master Clock

Prescale

PRE[1:0]

AMCLK = MCLK/1 (default)

AMCLK = MCLK/2

AMCLK = MCLK/4

AMCLK = MCLK/8

AMCLK

MCLK

PRESCALE

-------------------------------

Xtal Oscillator

MCLK

OSC1

OSC2

Multiplexer

OUT

1/PRESCALE

1/4

1/OSR

AMCLK

DMCLK

DRCLK

Clock Divider

OSR<2:0>

PRE<1:0>

CLKEXT

Multiplexer

OUT

MODE

SCK

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